1. Field of the Invention:
The present invention relates generally to integrated circuit memory devices, and more specifically to a circuit and method for detecting parity in memory devices.
2. Description of the Prior Art:
As is well known, occasional errors can occur in data stored in semiconductor memory devices. These errors can be caused by, for example, the malfunction of marginal active devices in an integrated circuit chip, electronic perturbations such as caused by power supply problems, and ionization caused by events such as alpha particle strikes. In most cases, the occurrence of these errors is essentially random. One common method used to detect the occurrence of such random errors is the generation and detection of a parity bit.
In its most common form, 1 parity bit is provided for each eight data bits, or for some other relatively small group of bits. Parity is defined as being odd or even, with the parity bit being assigned a value of 1 or 0 so that the number of ones in the data-plus-parity bits is either odd or even according to the defined parity scheme. This parity scheme allows for the detection of single bit errors, but will not detect two bit errors. In addition, no error correction is provided. Such a single bit parity detection scheme provides a good tradeoff between low cost and adequate error protection for most applications. This is true primarily because of the high reliability of semiconductor memory devices.
One type of memory used in computer systems is a cache memory. This is a relatively small, fast memory which resides in the system between the central processor and main system memory. Cache memory include data memory fields for storing data cached from system memory, and tag memory fields for storing the addresses corresponding to the data stored in the data cache. Like other memories, cache memories typically include parity checking.
Some cache tag memories, which can be implemented as single integrated circuit devices in some cases, have design considerations which render standard parity checking schemes inadequate. These types of memories allow for clearing the entire tag memory by resetting a particular bit position, referred to as the valid bit, for each storage location within the memory. In certain integrated circuit devices, all of the valid bits within the tag memory can be reset simultaneously in a single operation. This is sometimes referred to as a flash clear operation. Resetting 1 bit within each entry will invalidate the parity checking scheme, since parity checking of all tag memory entries and subsequent setting or resetting of the parity bit for each entry cannot be performed simultaneously on all entries in the memory.
It would be desirable to provide a parity checking scheme for these types of devices which provides complete parity coverage for all bits of the device, and which does not generate false parity errors.